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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. features ? 100 percent bus utilization no wait cycles between read and write internal self-timed write cycle individual byte write control single read/write control pin clock controlled, registered address, data and control interleaved or linear burst sequence control using mode input three chip enables for simple depth expansion and address pipelining power down mode common data inputs and data outputs cke pin to enable clock and suspend operation jedec 165-ball pbga and 209-ball (x72) pbga packages power supply: nvp: v dd 2.5v ( 5%), v ddq 2.5v ( 5%) nlp: v dd 3.3v ( 5%), v ddq 3.3v/2.5v ( 5%) jtag boundary scan for pbga packages industrial temperature available description the 36 meg 'nlp/nvp' product family feature high-speed, low-power synchronous static rams designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. they are organized as 512k words by 72 bits and 1024k words by 36 bits, fabricated with issi 's advanced cmos technology. incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. this device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. operations may be suspended and all synchronous inputs ignored when clock enable, cke is high. in this state the internal device will hold their previous values. all read, write and deselect cycles are initiated by the adv input. when the adv is high the internal burst counter is incremented. new external addresses can be loaded when adv is low. write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when we is low. separate byte enables allow individual bytes to be written. a burst mode pin (mode) defines the order of the burst sequence. when tied high, the interleaved burst sequence is selected. when tied low, the linear burst sequence is selected. 512k x 72, 1024k x 36 36mb, pipeline 'no wait' state bus sram advance information august 2003 fast access time symbol p arameter -250 -200 units t kq clock access time 2.6 3.1 ns t kc cycle time 4 5 ns frequency 250 200 mhz
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? block diagram adv we } bw ? x (x=a,b,c,d or a,b) ce ce2 ce2 control logic 512kx72; 1024kx36; memory array write address register write address register control logic output register buffer address register x 72: a [0:18] or x 36: a [0:19] clk cke a2-a19 or a2-a20 a0-a1 a'0-a'1 burst address counter mode data-in register data-in register control register oe zz 72 or 36 k k dqx/dqpx k k
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? bottom view 209-ball, 14 mm x 22 mm bga bottom view 165-ball, 13 mm x 15mm bga bottom view 119-ball, 14 mm x 22 mm bga
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? pin configuration ? 512k x 72, 209-ball pbga (top view) 1234567891011 a dqg dqg a ce2 a adv a ce2 a dqb dqb b dqg dqg bw c bw gnc we a bw b bw f dqb dqb c dqg dqg bw h bw dnc ce nc bw e bw a dqb dqb d dqg dqg v ss nc nc oe nc nc v ss dqb dqb e dqpg dqpc v ddq v ddq v dd v dd v dd v ddq v ddq dqpf dqpb f dqc dqc v ss v ss v ss nc v ss v ss v ss dqf dqf g dqc dqc v ddq v ddq v dd nc v dd v ddq v ddq dqf dqf h dqc dqc v ss v ss v ss nc v ss v ss v ss dqf dqf j dqc dqc v ddq v ddq v dd nc v dd v ddq v ddq dqf dqf k nc nc clk nc v ss cke v ss nc nc nc nc l dqh dqh v ddq v ddq v dd nc v dd v ddq v ddq dqa dqa m dqh dqh v ss v ss v ss nc v ss v ss v ss dqa dqa n dqh dqh v ddq v ddq v dd nc v dd v ddq v ddq dqa dqa p dqh dqh v ss v ss v ss zz v ss v ss v ss dqa dqa r dqpd dqph v ddq v ddq v dd v dd v dd v ddq v ddq dqpa dqpe t dqd dqd v ss nc nc mode nc nc v ss dqe dqe u dqd dqd nc a nc a a a nc dqe dqe v dqd dqd a a a a1 a a a dqe dqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe 11 x 19 ball bga?14 x 22 mm 2 body?1 mm ball pitch pin descriptions symbol pin name a synchronous address inputs a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. adv synchronous burst address advance bw a- bw h synchronous byte write enable ce , ce2 , ce2 synchronous chip enable clk synchronous clock cke clock enable dqx synchronous data input/output dqpx parity data i/o v ss ground mode bu rst sequence selection oe output enable tck, tdi jtag pins tdo, tms v dd 3.3v/2.5v power supply v ddq i solated output buffer supply: 3.3v/2.5v we write enable zz snooze enable
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? pin configuration ? 1024k x 36, 165-ball pbga (top view) 1234567891011 anc a ce bw c bw b ce 2 cke adv a a nc b nc a ce2 bw d bw a clk we oe aanc c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb h nc vdd nc v dd v ss v ss v ss v dd nc nc zz j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa n dqpd nc v ddq v ss nc nc nc v ss v ddq nc dqpa p nc nc a a tdi a1* tdo a a a nc r mode a a a tms a0* tck a a a a note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired . pin descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke clock enable ce synchronous chip select ce 2 synchronous chip select ce2 synchronous chip select bw x (x=a-d) synchronous byte write inputs oe output enable zz power sleep mode mode burst sequence selection tck, tdi jtag pins tdo, tms v dd 3.3v/2.5v power supply nc no connect dqx data inputs/outputs dqpx parity data i/o v ddq isolated output power supply 3.3v/2.5v v ss ground
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? synchronous truth table (1) address operation used ce ce ce ce ce ce2 ce ce ce ce ce 2 adv we we we we we bw bw bw bw bw x oe oe oe oe oe cke cke cke cke cke clk not selected n/a h x x l x x x l not selected n/a x l x l x x x l not selected n/a x x h l x x x l not selected continue n/a x x x h x x x l begin burst read external address l h l l h x l l continue burst read next address x x x h x x l l nop/dummy read external address l h l l h x h l dummy read next address x x x h x x h l begin burst write external address l h l l l l x l continue burst write next address x x x h x l x l nop/write abort n/a l h l l l h x l write abort next address x x x h x h x l ignore clock current address x x x x x x x h notes: 1. "x" means don't care. 2. the rising edge of clock is symbolized by 3. a continue deselect cycle can only be entered if a deselect cycle is executed first. 4. we = l means write operation in write truth table. we = h means read operation in write truth table. 5. operation finally depends on status of asynchronous pins (zz and oe ). burst read deselect burst write begin read begin write read write read write burst burst burst ds ds ds read ds ds read write write burst burst write read state diagram
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? truth table (1) operation zz oe oe oe oe oe i/o status sleep mode h x high-z read ll dq l h high-z write l x din, high-z deselected l x high-z notes: 1. x means "don't care". 2. for write cycles following read cycles, the output buffers must be disabled with oe , otherwise data bus contention will occur. 3. sleep mode means power sleep mode where stand-by current does not depend on cycle time. 4. deselected means power sleep mode where stand-by current depends on cycle time. write truth table (x36) operation we we we we we bw bw bw bw bw a bw bw bw bw bw b bw bw bw bw bw c bw bw bw bw bw d read h x x x x write byte a l l h h h write byte b l h l h h write byte c l h h l h write byte d l h h h l write all bytes l l l l l write abort/nop l h h h h notes : 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk.
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? interleaved burst address table (mode = v dd or nc) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 write truth table (x72) operation we we we we we bw bw bw bw bw a bw bw bw bw bw b bw bw bw bw bw c bw bw bw bw bw d bw bw bw bw bw e bw bw bw bw bw f bw bw bw bw bw g bw bw bw bw bw h read h x x x x x x x x write byte a l l h h h h h h h write byte b l h l h h h h h h write byte c l h h l h h h h h write byte d l h h h l h h h h write byte e l h h h h l h h h write byte f l h h h h h l h h write byte g l h h h h h h l h write byte h l h h h h h h h l write all bytes l l l l l l l l l write abort/nop l h h h h h h h h notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? linear burst address table (mode = v ss ) absolute maximum ratings (1) symbol parameter value unit t stg storage temperature ?65 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to v ss for i/o pins ?0.5 to v ddq + 0.3 v v in voltage relative to v ss for ?0.3 to 4.6 v for address and control inputs notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1 operating range (is61nlpx) range ambient temperature v dd v ddq commercial 0c to +70c 3.3v 5% 3.3v / 2.5v 5% industrial -40c to +85c 3.3v 5% 3.3v / 2.5v 5%
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? power supply characteristics (1) (over operating range) -250 -200 max max symbol parameter test conditions temp. range x36 x72 x36 x72 uni t i cc ac operating device selected, com. 500 600 500 550 ma supply current oe = v ih , zz v il , ind. 550 650 550 600 all inputs 0.2v or v dd ? 0.2v, cycle time t kc min. i sb standby current device deselected, com. 150 150 150 150 ma ttl input v dd = max., ind. ? ? 150 150 all inputs v il or v ih , zz v il , f = max. i sbi standby current device deselected, com. 100 100 100 100 ma cmos input v dd = max., ind. ? ? 115 115 v in v ss + 0.2v or v dd ? 0.2v, f = 0 i sb 2 sleep mode zz > v ih com. 60 60 60 60 ma ind. ? ? 75 75 note: 1. mode pin has an internal pullup and should be tied to v dd or v ss . it exhibits 100a maximum leakage current when tied to v ss + 0.2v or v dd ? 0.2v. dc electrical characteristics (over operating range) 3.3v 2.5v symbol parameter test conditions min. max. min. max. unit v oh output high voltage i oh = ?4.0 ma (3.3v) 2.4 ? 2.0 ? v i oh = ?1.0 ma (2.5v) v ol output low voltage i ol = 8.0 ma (3.3v) ? 0.4 ? 0.4 v i ol = 1.0 ma (2.5v) v ih input high voltage 2.0 v dd + 0.3 1.7 v dd + 0.3 v v il input low voltage ?0.3 0.8 ?0.3 0.7 v i li input leakage current v ss v in v dd (1) ?5 5 ?5 5 a i lo output leakage current v ss v out v ddq , oe = v ih ?5 5 ?5 5 a operating range (is61nvpx) range ambient temperature v dd v ddq commercial 0c to +70c 2.5v 5% 2.5v 5% industrial -40c to +85c 2.5v 5% 2.5v 5%
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 317 ? 5 pf including jig and scope 351 ? output +3.3v figure 1 figure 2 capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. 3.3v i/o output load equivalent 1.5v output zo= 50 ? 50 ?
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 3 and 4 z o = 50 ? 1.25v 50 ? output 1,667 ? 5 pf including jig and scope 1,538 ? output +2.5v figure 3 figure 4 2.5v i/o output load equivalent
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? read/write cycle switching characteristics (1) (over operating range) -250 -200 symbol parameter min. max. min. max. unit fmax clock frequency ? 250 ? 200 mhz t kc cycle time 4.0 ? 5 ? ns t kh clock high time 1.7 ? 2 ? ns t kl clock low time 1.7 ? 2 ? ns t kq clock access time ? 2.6 ? 3.1 ns t kqx (2) clock high to output invalid 0.8 ? 1.5 ? ns t kqlz (2,3) clock high to output low-z 0.8 ? 1 ? ns t kqhz (2,3) clock high to output high-z ? 2.6 ? 3.0 ns t oeq output enable to output valid ? 2.6 ? 3.1 ns t oelz (2,3) output enable to output low-z 0 ? 0 ? ns t oehz (2,3) output disable to output high-z ? 2.6 ? 3.0 ns t as address setup time 1.2 ? 1.4 ? ns t ws read/write setup time 1.2 ? 1.4 ? ns t ces chip enable setup time 1.2 ? 1.4 ? ns t se clock enable setup time 1.2 ? 1.4 ? ns t advs address advance setup time 1.2 ? 1.4 ? ns t ds data setup time 1.2 ? 1.4 ? ns t ah address hold time 0.3 ? 0.4 ? ns t he clock enable hold time 0.3 ? 0.4 ? ns t wh write hold time 0.3 ? 0.4 ? ns t ceh chip enable hold time 0.3 ? 0.4 ? ns t advh address advance hold time 0.3 ? 0.4 ? ns t dh data hold time 0.3 ? 0.4 ? ns t pds zz high to power down ? 2 ? 2 cyc t pus zz low to power down ? 2 ? 2 cyc notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? sleep mode timing sleep mode electrical characteristics symbol parameter cond itions min. max. unit i sb 2 current during sleep mode zz v ih 60 ma t pds zz active to input ignored 2 cycle t pus zz inactive to input sampled 2 cycle t zzi zz active to sleep current 2 cycle t rzzi zz inactive to exit sleep current 0 ns don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? read cycle timing t ds clk adv address write cke ce oe data out a1 a2 a3 t kh t kl t kc q3-3 q3-4 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 don't care undefined notes: write = l means we = l and bw x = l we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l t oehz t se t he t as t ah t ws t wh t ces t ceh t advs t advh t kqhz t kq t oeq t oehz q1-1
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? write cycle timing t ds t dh clk adv address write cke ce oe data in data out a1 a2 a3 t kh t kl t kc t se t he d3-3 d3-4 d3-2 d3-1 d2-4 d2-3 d2-2 d2-1 d1-1 don't care undefined notes: write = l means we = l and bw x = l we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l t oehz q0-3 q0-4
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? single read/write cycle timing clk cke address write ce adv oe data out data in d5 t se t he t kh t kl t kc don't care undefined notes: write = l means we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l d2 t oelz t oeq a1 a2 a3 a4 a5 a6 a7 a8 a9 q1 q3 q4 q6 q7 t ds t dh
18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? cke cke cke cke cke operation timing a1 a2 a3 a4 a5 a6 q1 q3 q4 clk cke address write ce adv oe data out data in d2 t se t he t kh t kl t kc t kqlz t kqhz t kq t dh t ds don't care undefined notes: write = l means we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? ce ce ce ce ce operation timing don't care undefined clk cke address write ce adv oe data out data in t se t he t kh t kl t kc notes: write = l means we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l d5 d3 t dh t ds t oelz t oeq q1 q2 q4 t kqhz t kqlz t kq a1 a2 a3 a4 a5
20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? ieee 1149.1 serial boundary scan (jtag) the is61nlp and is61nvp have a serial boundary scan test access port (tap) in the pbga package only. (not available in tqfp package.) this port operates in accor- dance with ieee standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because they place added delay in the critical speed path of the sram. the tap controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 2.5v i/o logic levels. disabling the jtag feature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be disconnected. they may alternately be connected to v cc through a pull-up resistor. tdo should be left disconnected. on power-up, the device will start in a reset state which will not interfere with the device operation. test access port (tap) - test clock the test clock is only used with the tap controller. all inputs are captured on the rising edge of tck and outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. this pin may be left disconnected if the tap is not used. the pin is internally pulled up, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information to the registers and can be connected to the input of any register. the register between tdi and tdo is chosen by the instruction loaded into the tap instruction register. for information on instruction register loading, see the tap controller state diagram. tdi is internally pulled up and can be disconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. 31 30 29 . . . 2 1 0 2 1 0 0 x . . . . . 2 1 0 bypass register instruction register identification register boundary scan register* tap controller selection circuitry selection circuitry tdo tdi tck tms tap controller block diagram
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending on the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck and tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power-up, the tap is internally reset to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry . only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins. (see tap controller block diagram) at power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as previously described. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is ex- ecuted. boundary scan register the boundary scan register is connected to all input and output pins on the sram . several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 configuration has a 75-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample-z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded to the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has vendor code and other information described in the identification register definitions table. scan register sizes register bit size bit size name (x36) (x72) instruction 3 3 bypass 1 1 id 32 32 boundary scan 75 tbd identification register definitions instruction field description 512k x 72 1024k x 36 revision number (31:28) r eserved for version number. xxxx xxxx device depth (27:23) defines depth of sram. 512k or 1m 00110 00111 device width (22:18) defines width of the sram.x72, x36 or x18 00101 00100 issi device id (17:12) reserved for future use. xxxx xxxxx issi jedec id (11:1) allows unique identification of sram vendor. 0011010101 00011010101 id register presence (0) indicate the presence of an id register. 1 1
22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? tap instruction set eight instructions are possible with the three-bit instruction register and all combinations are listed in the instruction code table. three instructions are listed as reserved and should not be used and the other five instructions are described below. the tap controller used in this sram is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. the tap controller cannot be used to load address, data or control signals and cannot preload the input or output buffers. the sram does not implement the 1149.1 com- mands extest or intest or the preload portion of sample/preload ; instead it performs a capture of the inputs and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted from the instruction register through the tdi and tdo pins. to execute an instruction once it is shifted in, the tap controller must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. because extest is not implemented in the tap controller, this device is not 1149.1 standard compliant. the tap controller recognizes an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is a difference between the instructions, unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample-z the sample-z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not imple- mented, so the tap controller is not fully 1149.1 compli- ant. when the sample/preload instruction is loaded to the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. it is important to realize that the tap controller clock operates at a frequency up to 10 mhz, while the sram clock runs more than an order of magnitude faster. because of the clock frequency differences, it is possible that during the capture-dr state, an input or output will under-go a transition. the tap may attempt a signal capture while in transition (metastable state). the device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. to guarantee that the boundary scan register will capture the correct signal value, the sram signal must be stabilized long enough to meet the tap controller?s capture set-up plus hold times (t cs and t ch ). to insure that the sram clock input is captured correctly, designs need a way to stop (or slow) the clock during a sample/ preload instruction. if this is not an issue, it is possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? instruction codes code instruction description 000 extest captures the input/output ring contents. places the boundary scan register between the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. 001 idcode loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. 010 sample-z captur es the input/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. 011 reserved do not use: this instruction is reserved for future use. 100 sample/preload captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 reserved do not use: this instruction is reserved for future use. 110 reserved do not use: this instruction is reserved for future use. 111 bypass places the bypass register between tdi and tdo. this operation does not affect sram operation. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test/idle 11 1 11 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 10 tap controller state diagram
24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? tap electrical characteristics over the operating range (1,2) symbol parameter test conditions min. max. units v oh1 output high voltage i oh = ?2.0 ma 1.7 ? v v oh2 output high voltage i oh = ?100 a 2.1 ? v v ol1 output low voltage i ol = 2.0 ma ? 0.7 v v ol2 output low voltage i ol = 100 a ? 0.2 v v ih input high voltage 1.7 v dd +0.3 v v il input low voltage ?0.3 0.7 v i x input leakage current v ss v i v ddq ?10 10 a notes: 1. all voltage referenced to ground. 2. overshoot: v ih (ac) v dd +1.5v for t t tcyc /2, undershoot: v il (ac) 0.5v for t t tcyc /2, power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ms. tap ac electrical characteristics (1,2) (over operating range) symbol parameter min. max. unit t tcyc tck clock cycle time 100 ? ns f tf tck clock frequency ? 10 mhz t th tck clock high 40 ? ns t tl tck clock low 40 ? ns t tmss tms setup to tck clock rise 10 ? ns t tdis tdi setup to tck clock rise 10 ? ns t cs capture setup to tck rise 10 ? ns t tmsh tms hold after tck clock rise 10 ? ns t tdih tdi hold after clock rise 10 ? ns t ch capture hold after clock rise 10 ? ns t tdov tck low to tdo valid ? 20 ns t tdox tck low to tdo invalid 0 ? ns notes: 1. both t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? don't care undefined tck tms tdi tdo t thtl t tlth t thth t mvth t thmx t dvth t thdx 1 2 3 4 5 6 t tlox t tlov tap timing 20 pf tdo gnd 50 ? vtrig z 0 = 50 ? tap output load equivalent tap ac test conditions (2.5v/3.3v) input pulse levels 0 to 2.5v/0 to 3.0v input rise and fall times 1ns input timing reference levels 1.25v/1.5v output reference levels 1.25v/1.5v test load termination supply voltage 1.25v/1.5v vtrig 1.25v/1.5v
26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? 209 boundary scan order (512k x 72) tbd
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 27 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? 165 pbga boundary scan order (x 36) signal bump signal bump signal bump signal bump bit # name id bit # name id bit # name id bit # name id 1 mode 1r 21 dqb 11g 41 nc 1a 61 dqd 1j 2 nc 6n 22 dqb 11f 42 ce 2 6a 62 dqd 1k 3 nc 11p 23 dqb 11e 43 bw a 5b 63 dqd 1l 4 a 8p 24 dqb 11d 44 bw b 5a 64 dqd 1m 5 a 8r 25 dqb 10g 45 bw c 4a 65 dqd 2j 6 a 9r 26 dqb 10f 46 bw d 4b 66 dqd 2k 7 a 9p 27 dqb 10e 47 ce2 3b 67 dqd 2l 8 a 10p 28 dqb 10d 48 ce 3a 68 dqd 2m 9 a 10r 29 dqb 11c 49 a 2a 69 dqd 1n 10 a 11r 30 nc 11a 50 a 2b 70 a 3p 11 zz 11h 31 a 10a 51 nc 1b 71 a 3r 12 dqa 11n 32 a 10b 52 dqc 1c 72 a 4r 13 dqa 11m 33 a 9a 53 dqc 1d 73 a 4p 14 dqa 11l 34 a 9b 54 dqc 1e 74 a1 6p 15 dqa 11k 35 adv 8a 55 dqc 1f 75 a0 6r 16 dqa 11j 36 oe 8b 56 dqc 1g 17 dqa 10m 37 cke 7a 57 dqc 2d 18 dqa 10l 38 we 7b 58 dqc 2e 19 dqa 10k 39 clk 6b 59 dqc 2f 20 dqa 10j 40 nc 11b 60 dqc 2g
28 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? ordering information (3.3v core/2.5v- 3.3v i/o) commercial range: 0c to +70c access time order part number package 512kx72 250 is61nlp51272-250b1 209 pbga 200 is61nlp51272-200b1 209 pbga 1024kx36 250 is61nlp102436-250b3 165 pbga 200 is61nlp102436-200b3 165 pbga industrial range: -40c to +85c access time order part number package 512kx72 250 is61nlp51272-250b1i 209 pbga 200 is61nlp51272-200b1i 209 pbga 1024kx36 250 is61nlp102436-250b3i 165 pbga 200 is61nlp102436-200b3i 165 pbga
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 29 rev. 00a 08/26/03 is61nlp51272/is61nvp51272 is61nlp102436/is61nvp102436 issi ? ordering information (2.5v core/2.5v i/o) commercial range: 0c to +70c access time order part number package 512kx72 250 IS61NVP51272-250B1 209 pbga 200 is61nvp51272-200b1 209 pbga 1024kx36 250 is61nvp102436-250b3 165 pbga 200 is61nvp102436-200b3 165 pbga industrial range: -40c to +85c access time order part number package 512kx72 250 is61nvp51272-250bi1 209 pbga 200 is61nvp51272-200bi1 209 pbga 1024kx36 250 is61nvp102436-250b3i 165 pbga 200 is61nvp102436-200b3i 165 pbga
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 08/22/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. mini ball grid array - 209 ball bga package code: b (14 mm x 22mm body, 1.0 mm ball pitch) notes: 1. controlling dimensions are in millimeters. 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 a b c d e f g h j k l m n p r t u v y a b c d e f g h j k l m n p r t u v y b (209x) e e a1 a2 a3 seating plane e dd1 e1 a millimeters inches sym. min. typ. max. min. typ. max. n0. leads 209 a ? ? 1.95 ? ? 0.077 a1 0.40 0.50 0.60 0.016 0.020 0.024 a2 ? 0.54 ? ? 0.021 ? a3 0.65 0.70 0.75 0.026 0.028 0.030 d 21.90 22.00 22.10 0.862 0.866 0.870 d1 18.00 bsc 0.709 bsc e 13.90 14.00 14.10 0.547 0.551 0.555 e1 10.00 bsc 0.394 bsc e 1.00bsc 0.039bsc b 0.50 0.60 0.70 0.020 0.024 0.028
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 06/11/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 11 10 9 8 7 6 5 4 3 2 1 a1 corner bottom view d d1 e e e1 e 1 2 3 4 5 6 7 8 9 10 11 a1 corner top view a2 a a1 b (165x) ball grid array package code: b (165-pin) notes: 1. controlling dimensions are in millimeters. bga - 13mm x 15mm millimeters inches sym. min. nom. max. min. nom. max. n0. leads 165 165 a ? ? 1.20 ? ? 0.047 a1 0.25 0.33 0.40 0.010 0.013 0.016 a2 ? 0.79 ? ? 0.031 ? d 14.90 15.00 15.10 0.587 0.591 0.594 d1 13.90 14.00 14.10 0.547 0.551 0.555 e 12.90 13.00 13.10 0.508 0.512 0.516 e1 9.90 10.00 10.10 0.390 0.394 0.398 e? 1.00 ? ? 0.039 ? b 0.40 0.45 0.50 0.016 0.018 0.020

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